/** @file
 * Copyright (c) 2020-2023, Arm Limited or its affiliates. All rights reserved.
 * SPDX-License-Identifier : Apache-2.0

 * Licensed under the Apache License, Version 2.0 (the "License");
 * you may not use this file except in compliance with the License.
 * You may obtain a copy of the License at
 *
 *  http://www.apache.org/licenses/LICENSE-2.0
 *
 * Unless required by applicable law or agreed to in writing, software
 * distributed under the License is distributed on an "AS IS" BASIS,
 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
 * See the License for the specific language governing permissions and
 * limitations under the License.
**/

/** Begin config **/

/* Settings */
#define PLATFORM_OVERRIDE_PRINT_LEVEL  0x3     //The permissible levels are 1,2,3,4 and 5


/* MMU PGT config parameters */
#define PLATFORM_PAGE_SIZE              0x1000
#define PLATFORM_OVERRIDE_MMU_PGT_IAS   48
#define PLATFORM_OVERRIDE_MMU_PGT_OAS   48

/* PCIe BAR config parameters*/
#define PLATFORM_OVERRIDE_PCIE_BAR64_VAL   0x4000100000
#define PLATFORM_OVERRIDE_RP_BAR64_VAL     0x4000000000
#define PLATFORM_OVERRIDE_PCIE_BAR32NP_VAL 0x60000000
#define PLATFORM_OVERRIDE_PCIE_BAR32P_VAL  0x60600000
#define PLATOFRM_OVERRIDE_RP_BAR32_VAL     0x60850000

/* HART platform config paramaters */
#define PLATFORM_OVERRIDE_PE_CNT           16
#define PLATFORM_OVERRIDE_PE0_INDEX        0x0
#define PLATFORM_OVERRIDE_PE0_MPIDR        0x0
#define PLATFORM_OVERRIDE_PE0_PMU_GSIV     0x17
#define PLATFORM_OVERRIDE_PE0_GMAIN_GSIV   0x19
#define PLATFORM_OVERRIDE_PE1_INDEX        0x1
#define PLATFORM_OVERRIDE_PE1_MPIDR        0x10000
#define PLATFORM_OVERRIDE_PE1_PMU_GSIV     0x17
#define PLATFORM_OVERRIDE_PE1_GMAIN_GSIV   0x19
#define PLATFORM_OVERRIDE_PE2_INDEX        0x2
#define PLATFORM_OVERRIDE_PE2_MPIDR        0x20000
#define PLATFORM_OVERRIDE_PE2_PMU_GSIV     0x17
#define PLATFORM_OVERRIDE_PE2_GMAIN_GSIV   0x19
#define PLATFORM_OVERRIDE_PE3_INDEX        0x3
#define PLATFORM_OVERRIDE_PE3_MPIDR        0x30000
#define PLATFORM_OVERRIDE_PE3_PMU_GSIV     0x17
#define PLATFORM_OVERRIDE_PE3_GMAIN_GSIV   0x19
#define PLATFORM_OVERRIDE_PE4_INDEX        0x4
#define PLATFORM_OVERRIDE_PE4_MPIDR        0x40000
#define PLATFORM_OVERRIDE_PE4_PMU_GSIV     0x17
#define PLATFORM_OVERRIDE_PE4_GMAIN_GSIV   0x19
#define PLATFORM_OVERRIDE_PE5_INDEX        0x5
#define PLATFORM_OVERRIDE_PE5_MPIDR        0x50000
#define PLATFORM_OVERRIDE_PE5_PMU_GSIV     0x17
#define PLATFORM_OVERRIDE_PE5_GMAIN_GSIV   0x19
#define PLATFORM_OVERRIDE_PE6_INDEX        0x6
#define PLATFORM_OVERRIDE_PE6_MPIDR        0x60000
#define PLATFORM_OVERRIDE_PE6_PMU_GSIV     0x17
#define PLATFORM_OVERRIDE_PE6_GMAIN_GSIV   0x19
#define PLATFORM_OVERRIDE_PE7_INDEX        0x7
#define PLATFORM_OVERRIDE_PE7_MPIDR        0x70000
#define PLATFORM_OVERRIDE_PE7_PMU_GSIV     0x17
#define PLATFORM_OVERRIDE_PE7_GMAIN_GSIV   0x19
#define PLATFORM_OVERRIDE_PE8_INDEX        0x8
#define PLATFORM_OVERRIDE_PE8_MPIDR        0x80000
#define PLATFORM_OVERRIDE_PE8_PMU_GSIV     0x17
#define PLATFORM_OVERRIDE_PE8_GMAIN_GSIV   0x19
#define PLATFORM_OVERRIDE_PE9_INDEX        0x9
#define PLATFORM_OVERRIDE_PE9_MPIDR        0x90000
#define PLATFORM_OVERRIDE_PE9_PMU_GSIV     0x17
#define PLATFORM_OVERRIDE_PE9_GMAIN_GSIV   0x19
#define PLATFORM_OVERRIDE_PE10_INDEX       0xA
#define PLATFORM_OVERRIDE_PE10_MPIDR       0xA0000
#define PLATFORM_OVERRIDE_PE10_PMU_GSIV    0x17
#define PLATFORM_OVERRIDE_PE10_GMAIN_GSIV  0x19
#define PLATFORM_OVERRIDE_PE11_INDEX       0xB
#define PLATFORM_OVERRIDE_PE11_MPIDR       0xB0000
#define PLATFORM_OVERRIDE_PE11_PMU_GSIV    0x17
#define PLATFORM_OVERRIDE_PE11_GMAIN_GSIV  0x19
#define PLATFORM_OVERRIDE_PE12_INDEX       0xC
#define PLATFORM_OVERRIDE_PE12_MPIDR       0xC0000
#define PLATFORM_OVERRIDE_PE12_PMU_GSIV    0x17
#define PLATFORM_OVERRIDE_PE12_GMAIN_GSIV  0x19
#define PLATFORM_OVERRIDE_PE13_INDEX       0xD
#define PLATFORM_OVERRIDE_PE13_MPIDR       0xD0000
#define PLATFORM_OVERRIDE_PE13_PMU_GSIV    0x17
#define PLATFORM_OVERRIDE_PE13_GMAIN_GSIV  0x19
#define PLATFORM_OVERRIDE_PE14_INDEX       0xE
#define PLATFORM_OVERRIDE_PE14_MPIDR       0xE0000
#define PLATFORM_OVERRIDE_PE14_PMU_GSIV    0x17
#define PLATFORM_OVERRIDE_PE14_GMAIN_GSIV  0x19
#define PLATFORM_OVERRIDE_PE15_INDEX       0xF
#define PLATFORM_OVERRIDE_PE15_MPIDR       0xF0000
#define PLATFORM_OVERRIDE_PE15_PMU_GSIV    0x17
#define PLATFORM_OVERRIDE_PE15_GMAIN_GSIV  0x19

/* IIC platform config parameters*/
#define PLATFORM_OVERRIDE_GIC_VERSION       0x3
#define PLATFORM_OVERRIDE_CORE_COUNT        0x4
#define PLATFORM_OVERRIDE_CLUSTER_COUNT     0x2
#define PLATFORM_OVERRIDE_GICC_COUNT        16
#define PLATFORM_OVERRIDE_GICD_COUNT        0x1
#define PLATFORM_OVERRIDE_GICC_GICRD_COUNT  0x0
#define PLATFORM_OVERRIDE_GICR_GICRD_COUNT  0x1
#define PLATFORM_OVERRIDE_GICITS_COUNT      0x6
#define PLATFORM_OVERRIDE_GICH_COUNT        0x1
#define PLATFORM_OVERRIDE_GICMSIFRAME_COUNT 0x0
#define PLATFORM_OVERRIDE_GICC_TYPE         0x1000
#define PLATFORM_OVERRIDE_GICD_TYPE         0x1001
#define PLATFORM_OVERRIDE_GICC_GICRD_TYPE   0x1002
#define PLATFORM_OVERRIDE_GICR_GICRD_TYPE   0x1003
#define PLATFORM_OVERRIDE_GICITS_TYPE       0x1004
#define PLATFORM_OVERRIDE_GICMSIFRAME_TYPE  0x1005
#define PLATFORM_OVERRIDE_GICH_TYPE         0x1006
#define PLATFORM_OVERRIDE_GICC_BASE         0x30000000
#define PLATFORM_OVERRIDE_GICD_BASE         0x30000000
#define PLATFORM_OVERRIDE_GICC_GICRD_BASE   0x0
#define PLATFORM_OVERRIDE_GICR_GICRD_BASE   0x301C0000
#define PLATFORM_OVERRIDE_GICH_BASE         0x2C010000
#define PLATFORM_OVERRIDE_GICITS0_BASE       0x30040000
#define PLATFORM_OVERRIDE_GICITS0_ID         0
#define PLATFORM_OVERRIDE_GICITS1_BASE       0x30080000
#define PLATFORM_OVERRIDE_GICITS1_ID         0x1
#define PLATFORM_OVERRIDE_GICITS2_BASE       0x300C0000
#define PLATFORM_OVERRIDE_GICITS2_ID         0x2
#define PLATFORM_OVERRIDE_GICITS3_BASE       0x30100000
#define PLATFORM_OVERRIDE_GICITS3_ID         0x3
#define PLATFORM_OVERRIDE_GICITS4_BASE       0x30140000
#define PLATFORM_OVERRIDE_GICITS4_ID         0x4
#define PLATFORM_OVERRIDE_GICITS5_BASE       0x30180000
#define PLATFORM_OVERRIDE_GICITS5_ID         0x5
#define PLATFORM_OVERRIDE_GICCIRD_LENGTH     0x0
#define PLATFORM_OVERRIDE_GICRIRD_LENGTH     (0x20000*8)

/*
 *Secure EL1 timer Flags, Non-Secure EL1 timer Flags, EL2 timer Flags,
 *and Virtual timer Flags all can have the same definition as follows.
 */
#define INTERRUPT_IS_LEVEL_TRIGGERED 0x0
#define INTERRUPT_IS_EDGE_TRIGGERED  0x1
#define INTERRUPT_IS_ACTIVE_HIGH     0x0
#define INTERRUPT_IS_ACTIVE_LOW      0x1

#define TIMER_MODE      INTERRUPT_IS_LEVEL_TRIGGERED
#define TIMER_POLARITY  INTERRUPT_IS_ACTIVE_LOW

#define TIMER_IS_SECURE     0x1

#define TIMER_IS_ALWAYS_ON_CAPABLE   0x1

/* Timer platform config parameters */
#define PLATFORM_OVERRIDE_S_EL1_TIMER_FLAGS     ((TIMER_POLARITY << 1) | (TIMER_MODE << 0))
#define PLATFORM_OVERRIDE_NS_EL1_TIMER_FLAGS    ((TIMER_POLARITY << 1) | (TIMER_MODE << 0))
#define PLATFORM_OVERRIDE_NS_EL2_TIMER_FLAGS    ((TIMER_POLARITY << 1) | (TIMER_MODE << 0))
#define PLATFORM_OVERRIDE_VIRTUAL_TIMER_FLAGS   ((TIMER_POLARITY << 1) | (TIMER_MODE << 0))
#define PLATFORM_OVERRIDE_S_EL1_TIMER_GSIV      0x1D
#define PLATFORM_OVERRIDE_NS_EL1_TIMER_GSIV     0x1E
#define PLATFORM_OVERRIDE_NS_EL2_TIMER_GSIV     0x1A
#define PLATFORM_OVERRIDE_VIRTUAL_TIMER_GSIV    0x1B
#define PLATFORM_OVERRIDE_EL2_VIR_TIMER_GSIV    28
#define PLATFORM_OVERRIDE_PLATFORM_TIMER_COUNT  0x2

#define PLATFORM_OVERRIDE_SYS_TIMER_TYPE        0x2001
#define PLATFORM_OVERRIDE_TIMER_TYPE            PLATFORM_OVERRIDE_SYS_TIMER_TYPE
#define PLATFORM_OVERRIDE_TIMER_COUNT           0x2
#define PLATFORM_OVERRIDE_TIMER_CNTCTL_BASE     0x2a810000

#define PLATFORM_OVERRIDE_TIMER_FRAME_NUM_0     0
#define PLATFORM_OVERRIDE_TIMER_CNTBASE_0       0x2a830000
#define PLATFORM_OVERRIDE_TIMER_CNTEL0BASE_0    0xFFFFFFFFFFFFFFFF
#define PLATFORM_OVERRIDE_TIMER_GSIV_0          0x6d
#define PLATFORM_OVERRIDE_TIMER_VIRT_GSIV_0     0x0
#define PLATFORM_OVERRIDE_TIMER_PHY_FLAGS_0     0x0
#define PLATFORM_OVERRIDE_TIMER_VIRT_FLAGS_0    0x0
#define PLATFORM_OVERRIDE_TIMER_CMN_FLAGS_0     ((TIMER_IS_ALWAYS_ON_CAPABLE << 1) | (!TIMER_IS_SECURE << 0))
#define PLATFORM_OVERRIDE_TIMER_FLAGS_0         ((PLATFORM_OVERRIDE_TIMER_CMN_FLAGS_0 << 16) | \
                                                 (PLATFORM_OVERRIDE_TIMER_VIRT_FLAGS_0 << 8) | \
                                                 (PLATFORM_OVERRIDE_TIMER_PHY_FLAGS_0))

#define PLATFORM_OVERRIDE_TIMER_FRAME_NUM_1     1
#define PLATFORM_OVERRIDE_TIMER_CNTBASE_1       0x2a820000
#define PLATFORM_OVERRIDE_TIMER_CNTEL0BASE_1    0xFFFFFFFFFFFFFFFF
#define PLATFORM_OVERRIDE_TIMER_GSIV_1          0x6c
#define PLATFORM_OVERRIDE_TIMER_VIRT_GSIV_1     0x0
#define PLATFORM_OVERRIDE_TIMER_PHY_FLAGS_1     0x0
#define PLATFORM_OVERRIDE_TIMER_VIRT_FLAGS_1    0x0
#define PLATFORM_OVERRIDE_TIMER_CMN_FLAGS_1     ((TIMER_IS_ALWAYS_ON_CAPABLE << 1) | (TIMER_IS_SECURE << 0))
#define PLATFORM_OVERRIDE_TIMER_FLAGS_1         ((PLATFORM_OVERRIDE_TIMER_CMN_FLAGS_1 << 16) | \
                                                 (PLATFORM_OVERRIDE_TIMER_VIRT_FLAGS_1 << 8) | \
                                                 (PLATFORM_OVERRIDE_TIMER_PHY_FLAGS_1))
#define PLATFORM_BM_TIMER_CNTFRQ         0x5F5E100

/* Watchdog platform config parameters */
#define WD_MODE     INTERRUPT_IS_LEVEL_TRIGGERED
#define WD_POLARITY INTERRUPT_IS_ACTIVE_HIGH

#define WD_IS_SECURE     0x1

#define PLATFORM_OVERRIDE_WD_TIMER_COUNT    0x2
#define PLATFORM_OVERRIDE_WD_REFRESH_BASE   0x2A450000
#define PLATFORM_OVERRIDE_WD_CTRL_BASE      0x2A440000
#define PLATFORM_OVERRIDE_WD_GSIV_0         0x6E
#define PLATFORM_OVERRIDE_WD_FLAGS_0        ((!WD_IS_SECURE << 2) | (WD_POLARITY << 1) | (WD_MODE << 0))
#define PLATFORM_OVERRIDE_WD_GSIV_1         0x6F
#define PLATFORM_OVERRIDE_WD_FLAGS_1        ((WD_IS_SECURE << 2) | (WD_POLARITY << 1) | (WD_MODE << 0))



/* PCIE platform config parameters */
#define PLATFORM_OVERRIDE_NUM_ECAM                1

/* Offset from the memory range to be accesed
 * Modify this macro w.r.t to the requirement */
#define MEM_OFFSET_SMALL   0x10
#define MEM_OFFSET_MEDIUM  0x1000

/* Platform config parameters for ECAM_0 */
#define PLATFORM_OVERRIDE_PCIE_ECAM_BASE_ADDR_0   0x1010000000
#define PLATFORM_OVERRIDE_PCIE_SEGMENT_GRP_NUM_0  0x0
#define PLATFORM_OVERRIDE_PCIE_START_BUS_NUM_0    0x0
#define PLATFORM_OVERRIDE_PCIE_END_BUS_NUM_0      0x8

#define PLATFORM_OVERRIDE_PCIE_ECAM_BASE_ADDR_1  0x1010000000
#define PLATFORM_OVERRIDE_PCIE_SEGMENT_GRP_NUM_1 0x0
#define PLATFORM_OVERRIDE_PCIE_START_BUS_NUM_1   0x40
#define PLATFORM_OVERRIDE_PCIE_END_BUS_NUM_1     0x7F

#define PLATFORM_BM_OVERRIDE_PCIE_MAX_BUS      0x9
#define PLATFORM_BM_OVERRIDE_PCIE_MAX_DEV      32
#define PLATFORM_BM_OVERRIDE_PCIE_MAX_FUNC     8

// This value is arbitrary and may have to be adjusted
#define PLATFORM_BM_OVERRIDE_MAX_IRQ_CNT       0xFFFF

#define PLATFORM_OVERRIDE_MAX_SID              24

#define PLATFORM_OVERRIDE_TIMEOUT              0
/* Define the Timeout values to be used */
#define PLATFORM_BM_OVERRIDE_TIMEOUT_LARGE         0x10000
#define PLATFORM_BM_OVERRIDE_TIMEOUT_MEDIUM        0x1000
#define PLATFORM_BM_OVERRIDE_TIMEOUT_SMALL         0x10

/* Sample macros for ECAM_1
 * #define PLATFORM_OVERRIDE_PCIE_ECAM_BASE_ADDR_1  0x00000000
 * #define PLATFORM_OVERRIDE_PCIE_SEGMENT_GRP_NUM_1 0x0
 * #define PLATFORM_OVERRIDE_PCIE_START_BUS_NUM_1   0x0
 * #define PLATFORM_OVERRIDE_PCIE_END_BUS_NUM_1     0x0
 */

/* PCIE device hierarchy table */

#define PLATFORM_PCIE_NUM_ENTRIES        21
#define PLATFORM_PCIE_P2P_NOT_SUPPORTED  1

#define PLATFORM_PCIE_DEV0_CLASSCODE     0x6040000
#define PLATFORM_PCIE_DEV0_VENDOR_ID     0x13B5
#define PLATFORM_PCIE_DEV0_DEV_ID        0xDEF
#define PLATFORM_PCIE_DEV0_BUS_NUM       0
#define PLATFORM_PCIE_DEV0_DEV_NUM       1
#define PLATFORM_PCIE_DEV0_FUNC_NUM      0
#define PLATFORM_PCIE_DEV0_SEG_NUM       0
#define PLATFORM_PCIE_DEV0_DMA_SUPPORT   1
#define PLATFORM_PCIE_DEV0_DMA_COHERENT  0
#define PLATFORM_PCIE_DEV0_P2P_SUPPORT   0
#define PLATFORM_PCIE_DEV0_DMA_64BIT     0
#define PLATFORM_PCIE_DEV0_BEHIND_SMMU   1
#define PLATFORM_PCIE_DEV0_ATC_SUPPORT   0

#define PLATFORM_PCIE_DEV1_CLASSCODE     0x6040000
#define PLATFORM_PCIE_DEV1_VENDOR_ID     0x13B5
#define PLATFORM_PCIE_DEV1_DEV_ID        0xDEF
#define PLATFORM_PCIE_DEV1_BUS_NUM       0
#define PLATFORM_PCIE_DEV1_DEV_NUM       2
#define PLATFORM_PCIE_DEV1_FUNC_NUM      0
#define PLATFORM_PCIE_DEV1_SEG_NUM       0
#define PLATFORM_PCIE_DEV1_DMA_SUPPORT   1
#define PLATFORM_PCIE_DEV1_DMA_COHERENT  0
#define PLATFORM_PCIE_DEV1_P2P_SUPPORT   0
#define PLATFORM_PCIE_DEV1_DMA_64BIT     0
#define PLATFORM_PCIE_DEV1_BEHIND_SMMU   1
#define PLATFORM_PCIE_DEV1_ATC_SUPPORT   0

#define PLATFORM_PCIE_DEV2_CLASSCODE     0x6040000
#define PLATFORM_PCIE_DEV2_VENDOR_ID     0x13B5
#define PLATFORM_PCIE_DEV2_DEV_ID        0xDEF
#define PLATFORM_PCIE_DEV2_BUS_NUM       0
#define PLATFORM_PCIE_DEV2_DEV_NUM       3
#define PLATFORM_PCIE_DEV2_FUNC_NUM      0
#define PLATFORM_PCIE_DEV2_SEG_NUM       0
#define PLATFORM_PCIE_DEV2_DMA_SUPPORT   1
#define PLATFORM_PCIE_DEV2_DMA_COHERENT  0
#define PLATFORM_PCIE_DEV2_P2P_SUPPORT   0
#define PLATFORM_PCIE_DEV2_DMA_64BIT     0
#define PLATFORM_PCIE_DEV2_BEHIND_SMMU   1
#define PLATFORM_PCIE_DEV2_ATC_SUPPORT   0

#define PLATFORM_PCIE_DEV3_CLASSCODE     0x6040000
#define PLATFORM_PCIE_DEV3_VENDOR_ID     0x13B5
#define PLATFORM_PCIE_DEV3_DEV_ID        0x0DEF
#define PLATFORM_PCIE_DEV3_BUS_NUM       0
#define PLATFORM_PCIE_DEV3_DEV_NUM       4
#define PLATFORM_PCIE_DEV3_FUNC_NUM      0
#define PLATFORM_PCIE_DEV3_SEG_NUM       0
#define PLATFORM_PCIE_DEV3_DMA_SUPPORT   1
#define PLATFORM_PCIE_DEV3_DMA_COHERENT  0
#define PLATFORM_PCIE_DEV3_P2P_SUPPORT   0
#define PLATFORM_PCIE_DEV3_DMA_64BIT     0
#define PLATFORM_PCIE_DEV3_BEHIND_SMMU   1
#define PLATFORM_PCIE_DEV3_ATC_SUPPORT   0

#define PLATFORM_PCIE_DEV4_CLASSCODE     0x1060101
#define PLATFORM_PCIE_DEV4_VENDOR_ID     0x0ABC
#define PLATFORM_PCIE_DEV4_DEV_ID        0xACED
#define PLATFORM_PCIE_DEV4_BUS_NUM       1
#define PLATFORM_PCIE_DEV4_DEV_NUM       0
#define PLATFORM_PCIE_DEV4_FUNC_NUM      0
#define PLATFORM_PCIE_DEV4_SEG_NUM       0
#define PLATFORM_PCIE_DEV4_DMA_SUPPORT   1
#define PLATFORM_PCIE_DEV4_DMA_COHERENT  0
#define PLATFORM_PCIE_DEV4_P2P_SUPPORT   0
#define PLATFORM_PCIE_DEV4_DMA_64BIT     0
#define PLATFORM_PCIE_DEV4_BEHIND_SMMU   1
#define PLATFORM_PCIE_DEV4_ATC_SUPPORT   0

#define PLATFORM_PCIE_DEV5_CLASSCODE     0xED000000
#define PLATFORM_PCIE_DEV5_VENDOR_ID     0x13B5
#define PLATFORM_PCIE_DEV5_DEV_ID        0xED01
#define PLATFORM_PCIE_DEV5_BUS_NUM       2
#define PLATFORM_PCIE_DEV5_DEV_NUM       0
#define PLATFORM_PCIE_DEV5_FUNC_NUM      0
#define PLATFORM_PCIE_DEV5_SEG_NUM       0
#define PLATFORM_PCIE_DEV5_DMA_SUPPORT   1
#define PLATFORM_PCIE_DEV5_DMA_COHERENT  0
#define PLATFORM_PCIE_DEV5_P2P_SUPPORT   0
#define PLATFORM_PCIE_DEV5_DMA_64BIT     0
#define PLATFORM_PCIE_DEV5_BEHIND_SMMU   1
#define PLATFORM_PCIE_DEV5_ATC_SUPPORT   0

#define PLATFORM_PCIE_DEV6_CLASSCODE     0xED000000
#define PLATFORM_PCIE_DEV6_VENDOR_ID     0x13B5
#define PLATFORM_PCIE_DEV6_DEV_ID        0xED01
#define PLATFORM_PCIE_DEV6_BUS_NUM       2
#define PLATFORM_PCIE_DEV6_DEV_NUM       0
#define PLATFORM_PCIE_DEV6_FUNC_NUM      1
#define PLATFORM_PCIE_DEV6_SEG_NUM       0
#define PLATFORM_PCIE_DEV6_DMA_SUPPORT   1
#define PLATFORM_PCIE_DEV6_DMA_COHERENT  0
#define PLATFORM_PCIE_DEV6_P2P_SUPPORT   0
#define PLATFORM_PCIE_DEV6_DMA_64BIT     0
#define PLATFORM_PCIE_DEV6_BEHIND_SMMU   0
#define PLATFORM_PCIE_DEV6_ATC_SUPPORT   0

#define PLATFORM_PCIE_DEV7_CLASSCODE     0x6040000
#define PLATFORM_PCIE_DEV7_VENDOR_ID     0x13B5
#define PLATFORM_PCIE_DEV7_DEV_ID        0xDEF
#define PLATFORM_PCIE_DEV7_BUS_NUM       3
#define PLATFORM_PCIE_DEV7_DEV_NUM       0
#define PLATFORM_PCIE_DEV7_FUNC_NUM      0
#define PLATFORM_PCIE_DEV7_SEG_NUM       0
#define PLATFORM_PCIE_DEV7_DMA_SUPPORT   1
#define PLATFORM_PCIE_DEV7_DMA_COHERENT  0
#define PLATFORM_PCIE_DEV7_P2P_SUPPORT   0
#define PLATFORM_PCIE_DEV7_DMA_64BIT     0
#define PLATFORM_PCIE_DEV7_BEHIND_SMMU   0
#define PLATFORM_PCIE_DEV7_ATC_SUPPORT   0

#define PLATFORM_PCIE_DEV8_CLASSCODE    0x6040000
#define PLATFORM_PCIE_DEV8_VENDOR_ID    0x13B5
#define PLATFORM_PCIE_DEV8_DEV_ID       0xDEF
#define PLATFORM_PCIE_DEV8_BUS_NUM      4
#define PLATFORM_PCIE_DEV8_DEV_NUM      0
#define PLATFORM_PCIE_DEV8_FUNC_NUM     0
#define PLATFORM_PCIE_DEV8_SEG_NUM      0
#define PLATFORM_PCIE_DEV8_DMA_SUPPORT  1
#define PLATFORM_PCIE_DEV8_DMA_COHERENT 0
#define PLATFORM_PCIE_DEV8_P2P_SUPPORT  0
#define PLATFORM_PCIE_DEV8_DMA_64BIT    0
#define PLATFORM_PCIE_DEV8_BEHIND_SMMU  0
#define PLATFORM_PCIE_DEV8_ATC_SUPPORT  0

#define PLATFORM_PCIE_DEV9_CLASSCODE    0x6040000
#define PLATFORM_PCIE_DEV9_VENDOR_ID    0x13B5
#define PLATFORM_PCIE_DEV9_DEV_ID       0xDEF
#define PLATFORM_PCIE_DEV9_BUS_NUM      4
#define PLATFORM_PCIE_DEV9_DEV_NUM      1
#define PLATFORM_PCIE_DEV9_FUNC_NUM     0
#define PLATFORM_PCIE_DEV9_SEG_NUM      0
#define PLATFORM_PCIE_DEV9_DMA_SUPPORT  1
#define PLATFORM_PCIE_DEV9_DMA_COHERENT 0
#define PLATFORM_PCIE_DEV9_P2P_SUPPORT  0
#define PLATFORM_PCIE_DEV9_DMA_64BIT    0
#define PLATFORM_PCIE_DEV9_BEHIND_SMMU  0
#define PLATFORM_PCIE_DEV9_ATC_SUPPORT  0

#define PLATFORM_PCIE_DEV10_CLASSCODE    0x6040000
#define PLATFORM_PCIE_DEV10_VENDOR_ID    0x13B5
#define PLATFORM_PCIE_DEV10_DEV_ID       0xDEF
#define PLATFORM_PCIE_DEV10_BUS_NUM      4
#define PLATFORM_PCIE_DEV10_DEV_NUM      2
#define PLATFORM_PCIE_DEV10_FUNC_NUM     0
#define PLATFORM_PCIE_DEV10_SEG_NUM      0
#define PLATFORM_PCIE_DEV10_DMA_SUPPORT  1
#define PLATFORM_PCIE_DEV10_DMA_COHERENT 0
#define PLATFORM_PCIE_DEV10_P2P_SUPPORT  0
#define PLATFORM_PCIE_DEV10_DMA_64BIT    0
#define PLATFORM_PCIE_DEV10_BEHIND_SMMU  0
#define PLATFORM_PCIE_DEV10_ATC_SUPPORT  0

#define PLATFORM_PCIE_DEV11_CLASSCODE    0x1060101
#define PLATFORM_PCIE_DEV11_VENDOR_ID    0x0ABC
#define PLATFORM_PCIE_DEV11_DEV_ID       0xACED
#define PLATFORM_PCIE_DEV11_BUS_NUM      5
#define PLATFORM_PCIE_DEV11_DEV_NUM      0
#define PLATFORM_PCIE_DEV11_FUNC_NUM     0
#define PLATFORM_PCIE_DEV11_SEG_NUM      0
#define PLATFORM_PCIE_DEV11_DMA_SUPPORT  1
#define PLATFORM_PCIE_DEV11_DMA_COHERENT 0
#define PLATFORM_PCIE_DEV11_P2P_SUPPORT  0
#define PLATFORM_PCIE_DEV11_DMA_64BIT    0
#define PLATFORM_PCIE_DEV11_BEHIND_SMMU  0
#define PLATFORM_PCIE_DEV11_ATC_SUPPORT  0

#define PLATFORM_PCIE_DEV12_CLASSCODE    0xED000000
#define PLATFORM_PCIE_DEV12_VENDOR_ID    0x13B5
#define PLATFORM_PCIE_DEV12_DEV_ID       0xED01
#define PLATFORM_PCIE_DEV12_BUS_NUM      6
#define PLATFORM_PCIE_DEV12_DEV_NUM      0
#define PLATFORM_PCIE_DEV12_FUNC_NUM     0
#define PLATFORM_PCIE_DEV12_SEG_NUM      0
#define PLATFORM_PCIE_DEV12_DMA_SUPPORT  1
#define PLATFORM_PCIE_DEV12_DMA_COHERENT 0
#define PLATFORM_PCIE_DEV12_P2P_SUPPORT  0
#define PLATFORM_PCIE_DEV12_DMA_64BIT    0
#define PLATFORM_PCIE_DEV12_BEHIND_SMMU  0
#define PLATFORM_PCIE_DEV12_ATC_SUPPORT  0

#define PLATFORM_PCIE_DEV13_CLASSCODE    0xED000000
#define PLATFORM_PCIE_DEV13_VENDOR_ID    0x13B5
#define PLATFORM_PCIE_DEV13_DEV_ID       0xED01
#define PLATFORM_PCIE_DEV13_BUS_NUM      6
#define PLATFORM_PCIE_DEV13_DEV_NUM      0
#define PLATFORM_PCIE_DEV13_FUNC_NUM     7
#define PLATFORM_PCIE_DEV13_SEG_NUM      0
#define PLATFORM_PCIE_DEV13_DMA_SUPPORT  1
#define PLATFORM_PCIE_DEV13_DMA_COHERENT 0
#define PLATFORM_PCIE_DEV13_P2P_SUPPORT  0
#define PLATFORM_PCIE_DEV13_DMA_64BIT    0
#define PLATFORM_PCIE_DEV13_BEHIND_SMMU  0
#define PLATFORM_PCIE_DEV13_ATC_SUPPORT  0

#define PLATFORM_PCIE_DEV14_CLASSCODE    0xFF000000
#define PLATFORM_PCIE_DEV14_VENDOR_ID    0x13B5
#define PLATFORM_PCIE_DEV14_DEV_ID       0xFF80
#define PLATFORM_PCIE_DEV14_BUS_NUM      7
#define PLATFORM_PCIE_DEV14_DEV_NUM      0
#define PLATFORM_PCIE_DEV14_FUNC_NUM     0
#define PLATFORM_PCIE_DEV14_SEG_NUM      0
#define PLATFORM_PCIE_DEV14_DMA_SUPPORT  1
#define PLATFORM_PCIE_DEV14_DMA_COHERENT 0
#define PLATFORM_PCIE_DEV14_P2P_SUPPORT  0
#define PLATFORM_PCIE_DEV14_DMA_64BIT    0
#define PLATFORM_PCIE_DEV14_BEHIND_SMMU  0
#define PLATFORM_PCIE_DEV14_ATC_SUPPORT  0

#define PLATFORM_PCIE_DEV15_CLASSCODE    0xFF000000
#define PLATFORM_PCIE_DEV15_VENDOR_ID    0x13B5
#define PLATFORM_PCIE_DEV15_DEV_ID       0xFF80
#define PLATFORM_PCIE_DEV15_BUS_NUM      7
#define PLATFORM_PCIE_DEV15_DEV_NUM      0
#define PLATFORM_PCIE_DEV15_FUNC_NUM     7
#define PLATFORM_PCIE_DEV15_SEG_NUM      0
#define PLATFORM_PCIE_DEV15_DMA_SUPPORT  1
#define PLATFORM_PCIE_DEV15_DMA_COHERENT 0
#define PLATFORM_PCIE_DEV15_P2P_SUPPORT  0
#define PLATFORM_PCIE_DEV15_DMA_64BIT    0
#define PLATFORM_PCIE_DEV15_BEHIND_SMMU  0
#define PLATFORM_PCIE_DEV15_ATC_SUPPORT  0

#define PLATFORM_PCIE_DEV16_CLASSCODE    0xFF000000
#define PLATFORM_PCIE_DEV16_VENDOR_ID    0x13B5
#define PLATFORM_PCIE_DEV16_DEV_ID       0xFF80
#define PLATFORM_PCIE_DEV16_BUS_NUM      8
#define PLATFORM_PCIE_DEV16_DEV_NUM      0
#define PLATFORM_PCIE_DEV16_FUNC_NUM     0
#define PLATFORM_PCIE_DEV16_SEG_NUM      0
#define PLATFORM_PCIE_DEV16_DMA_SUPPORT  1
#define PLATFORM_PCIE_DEV16_DMA_COHERENT 0
#define PLATFORM_PCIE_DEV16_P2P_SUPPORT  0
#define PLATFORM_PCIE_DEV16_DMA_64BIT    0
#define PLATFORM_PCIE_DEV16_BEHIND_SMMU  0
#define PLATFORM_PCIE_DEV16_ATC_SUPPORT  0

#define PLATFORM_PCIE_DEV17_CLASSCODE    0xFF000000
#define PLATFORM_PCIE_DEV17_VENDOR_ID    0x13B5
#define PLATFORM_PCIE_DEV17_DEV_ID       0xFF80
#define PLATFORM_PCIE_DEV17_BUS_NUM      8
#define PLATFORM_PCIE_DEV17_DEV_NUM      0
#define PLATFORM_PCIE_DEV17_FUNC_NUM     1
#define PLATFORM_PCIE_DEV17_SEG_NUM      0
#define PLATFORM_PCIE_DEV17_DMA_SUPPORT  1
#define PLATFORM_PCIE_DEV17_DMA_COHERENT 0
#define PLATFORM_PCIE_DEV17_P2P_SUPPORT  0
#define PLATFORM_PCIE_DEV17_DMA_64BIT    0
#define PLATFORM_PCIE_DEV17_BEHIND_SMMU  0
#define PLATFORM_PCIE_DEV17_ATC_SUPPORT  0

#define PLATFORM_PCIE_DEV18_CLASSCODE    0xED000001
#define PLATFORM_PCIE_DEV18_VENDOR_ID    0x13B5
#define PLATFORM_PCIE_DEV18_DEV_ID       0xED01
#define PLATFORM_PCIE_DEV18_BUS_NUM      0
#define PLATFORM_PCIE_DEV18_DEV_NUM      0x0F
#define PLATFORM_PCIE_DEV18_FUNC_NUM     0
#define PLATFORM_PCIE_DEV18_SEG_NUM      0
#define PLATFORM_PCIE_DEV18_DMA_SUPPORT  0
#define PLATFORM_PCIE_DEV18_DMA_COHERENT 0
#define PLATFORM_PCIE_DEV18_P2P_SUPPORT  1
#define PLATFORM_PCIE_DEV18_DMA_64BIT    0
#define PLATFORM_PCIE_DEV18_BEHIND_SMMU  1
#define PLATFORM_PCIE_DEV18_ATC_SUPPORT  0

#define PLATFORM_PCIE_DEV19_CLASSCODE    0x1060101
#define PLATFORM_PCIE_DEV19_VENDOR_ID    0x0ABC
#define PLATFORM_PCIE_DEV19_DEV_ID       0xACED
#define PLATFORM_PCIE_DEV19_BUS_NUM      0
#define PLATFORM_PCIE_DEV19_DEV_NUM      0x1E
#define PLATFORM_PCIE_DEV19_FUNC_NUM     0
#define PLATFORM_PCIE_DEV19_SEG_NUM      0
#define PLATFORM_PCIE_DEV19_DMA_SUPPORT  0
#define PLATFORM_PCIE_DEV19_DMA_COHERENT 0
#define PLATFORM_PCIE_DEV19_P2P_SUPPORT  1
#define PLATFORM_PCIE_DEV19_DMA_64BIT    0
#define PLATFORM_PCIE_DEV19_BEHIND_SMMU  1
#define PLATFORM_PCIE_DEV19_ATC_SUPPORT  0

#define PLATFORM_PCIE_DEV20_CLASSCODE    0xED000000
#define PLATFORM_PCIE_DEV20_VENDOR_ID    0x13B5
#define PLATFORM_PCIE_DEV20_DEV_ID       0xED01
#define PLATFORM_PCIE_DEV20_BUS_NUM      0
#define PLATFORM_PCIE_DEV20_DEV_NUM      0x1F
#define PLATFORM_PCIE_DEV20_FUNC_NUM     0
#define PLATFORM_PCIE_DEV20_SEG_NUM      0
#define PLATFORM_PCIE_DEV20_DMA_SUPPORT  0
#define PLATFORM_PCIE_DEV20_DMA_COHERENT 0
#define PLATFORM_PCIE_DEV20_P2P_SUPPORT  1
#define PLATFORM_PCIE_DEV20_DMA_64BIT    0
#define PLATFORM_PCIE_DEV20_BEHIND_SMMU  1
#define PLATFORM_PCIE_DEV20_ATC_SUPPORT  0

/* PERIPHERAL platform config parameters */
#define PLATFORM_OVERRIDE_PERIPHERAL_COUNT 3  //UART + USB + SATA

#define UART_ADDRESS                     0xF98DFE18
#define BASE_ADDRESS_ADDRESS_SPACE_ID    0x0
#define BASE_ADDRESS_REGISTER_BIT_WIDTH  0x20
#define BASE_ADDRESS_REGISTER_BIT_OFFSET 0x0
#define BASE_ADDRESS_ADDRESS_SIZE        0x3
#define BASE_ADDRESS_ADDRESS             0x2A400000
#define INTERFACE_TYPE                   8
#define UART_IRQ                         0
#define UART_BAUD_RATE                   0x7
#define UART_BAUD_RATE_BPS               115200
#define UART_CLK_IN_HZ                   24000000
#define UART_GLOBAL_SYSTEM_INTERRUPT     0x70
#define UART_PCI_DEVICE_ID               0xFFFF
#define UART_PCI_VENDOR_ID               0xFFFF
#define UART_PCI_BUS_NUMBER              0x0
#define UART_PCI_DEV_NUMBER              0x0
#define UART_PCI_FUNC_NUMBER             0x0
#define UART_PCI_FLAGS                   0x0
#define UART_PCI_SEGMENT                 0x0

/* IOVIRT platform config parameters */
#define IOVIRT_ADDRESS                0xF98DEB18
#define IORT_NODE_COUNT               13
#define NUM_ITS_COUNT                 5
#define IOVIRT_ITS_COUNT              1
#define IOVIRT_SMMUV3_COUNT           5
#define IOVIRT_RC_COUNT               1
#define IOVIRT_SMMUV2_COUNT           0
#define IOVIRT_NAMED_COMPONENT_COUNT  2
#define IOVIRT_PMCG_COUNT             0
#define IOVIRT_SMMUV3_0_BASE_ADDRESS  0x40000000
#define IOVIRT_SMMUV3_1_BASE_ADDRESS  0x42000000
#define IOVIRT_SMMUV3_2_BASE_ADDRESS  0x44000000
#define IOVIRT_SMMUV3_3_BASE_ADDRESS  0x46000000
#define IOVIRT_SMMUV3_4_BASE_ADDRESS  0x48000000
#define IOVIRT_SMMU_CTX_INT_OFFSET    0x0
#define IOVIRT_SMMU_CTX_INT_CNT       0x0
#define IOVIRT_RC_PCI_SEG_NUM         0x0
#define IOVIRT_RC_MEMORY_PROPERTIES   0x0
#define IOVIRT_RC_ATS_ATTRIBUTE       0x1

#define RC_MAP0_INPUT_BASE            0x0
#define RC_MAP0_ID_COUNT              0x8FFF
#define RC_MAP0_OUTPUT_BASE           0x30000
#define RC_MAP0_OUTPUT_REF            0x5A4
#define RC_MAP1_INPUT_BASE            0x900
#define RC_MAP1_ID_COUNT              0xFF
#define RC_MAP1_OUTPUT_BASE           0x30900
#define RC_MAP1_OUTPUT_REF            0x6D0
#define RC_MAP2_INPUT_BASE            0xA00
#define RC_MAP2_ID_COUNT              0xFF
#define RC_MAP2_OUTPUT_BASE           0x30A00
#define RC_MAP2_OUTPUT_REF            0x7FC
#define RC_MAP3_INPUT_BASE            0xB00
#define RC_MAP3_ID_COUNT              0xFF
#define RC_MAP3_OUTPUT_BASE           0x30B00
#define RC_MAP3_OUTPUT_REF            0x928

#define SMMUV3_0_ID_MAP0_INPUT_BASE   0x0
#define SMMUV3_0_ID_MAP0_ID_COUNT     0x0
#define SMMUV3_0_ID_MAP0_OUTPUT_BASE  0x80000
#define SMMUV3_0_ID_MAP0_OUTPUT_REF   0x18
#define SMMUV3_0_ID_MAP1_INPUT_BASE   0x30000
#define SMMUV3_0_ID_MAP1_ID_COUNT     0x8FF
#define SMMUV3_0_ID_MAP1_OUTPUT_BASE  0x30000
#define SMMUV3_0_ID_MAP1_OUTPUT_REF   0x18

#define SMMUV3_1_ID_MAP0_INPUT_BASE   0x0
#define SMMUV3_1_ID_MAP0_ID_COUNT     0x0
#define SMMUV3_1_ID_MAP0_OUTPUT_BASE  0x80000
#define SMMUV3_1_ID_MAP0_OUTPUT_REF   0x134
#define SMMUV3_1_ID_MAP1_INPUT_BASE   0x30900
#define SMMUV3_1_ID_MAP1_ID_COUNT     0xFF
#define SMMUV3_1_ID_MAP1_OUTPUT_BASE  0x30900
#define SMMUV3_1_ID_MAP1_OUTPUT_REF   0x134

#define SMMUV3_2_ID_MAP0_INPUT_BASE   0x0
#define SMMUV3_2_ID_MAP0_ID_COUNT     0x0
#define SMMUV3_2_ID_MAP0_OUTPUT_BASE  0x80000
#define SMMUV3_2_ID_MAP0_OUTPUT_REF   0x250
#define SMMUV3_2_ID_MAP1_INPUT_BASE   0x30A00
#define SMMUV3_2_ID_MAP1_ID_COUNT     0xFF
#define SMMUV3_2_ID_MAP1_OUTPUT_BASE  0x30A00
#define SMMUV3_2_ID_MAP1_OUTPUT_REF   0x250

#define SMMUV3_3_ID_MAP0_INPUT_BASE   0x0
#define SMMUV3_3_ID_MAP0_ID_COUNT     0x0
#define SMMUV3_3_ID_MAP0_OUTPUT_BASE  0x80000
#define SMMUV3_3_ID_MAP0_OUTPUT_REF   0x36C
#define SMMUV3_3_ID_MAP1_INPUT_BASE   0x30B00
#define SMMUV3_3_ID_MAP1_ID_COUNT     0xFF
#define SMMUV3_3_ID_MAP1_OUTPUT_BASE  0x30B00
#define SMMUV3_3_ID_MAP1_OUTPUT_REF   0x36C

#define SMMUV3_4_ID_MAP0_INPUT_BASE   0x0
#define SMMUV3_4_ID_MAP0_ID_COUNT     0x0
#define SMMUV3_4_ID_MAP0_OUTPUT_BASE  0x80000
#define SMMUV3_4_ID_MAP0_OUTPUT_REF   0x488
#define SMMUV3_4_ID_MAP1_INPUT_BASE   0x10000
#define SMMUV3_4_ID_MAP1_ID_COUNT     0x9
#define SMMUV3_4_ID_MAP1_OUTPUT_BASE  0x10000
#define SMMUV3_4_ID_MAP1_OUTPUT_REF   0x488
#define SMMUV3_4_ID_MAP2_INPUT_BASE   0x30000
#define SMMUV3_4_ID_MAP2_ID_COUNT     0x9
#define SMMUV3_4_ID_MAP2_OUTPUT_BASE  0x30000
#define SMMUV3_4_ID_MAP2_OUTPUT_REF   0x488

#define NAMED_COMP0_MAP0_INPUT_BASE   0x0
#define NAMED_COMP0_MAP0_ID_COUNT     0x0
#define NAMED_COMP0_MAP0_OUTPUT_BASE  0x10000
#define NAMED_COMP0_MAP0_OUTPUT_REF   0xA54
#define NAMED_COMP0_MAP1_INPUT_BASE   0x1
#define NAMED_COMP0_MAP1_ID_COUNT     0x0
#define NAMED_COMP0_MAP1_OUTPUT_BASE  0x10001
#define NAMED_COMP0_MAP1_OUTPUT_REF   0xA54
#define NAMED_COMP0_MAP2_INPUT_BASE   0x2
#define NAMED_COMP0_MAP2_ID_COUNT     0x0
#define NAMED_COMP0_MAP2_OUTPUT_BASE  0x10002
#define NAMED_COMP0_MAP2_OUTPUT_REF   0xA54
#define NAMED_COMP0_MAP3_INPUT_BASE   0x3
#define NAMED_COMP0_MAP3_ID_COUNT     0x0
#define NAMED_COMP0_MAP3_OUTPUT_BASE  0x10003
#define NAMED_COMP0_MAP3_OUTPUT_REF   0xA54
#define NAMED_COMP0_MAP4_INPUT_BASE   0x4
#define NAMED_COMP0_MAP4_ID_COUNT     0x0
#define NAMED_COMP0_MAP4_OUTPUT_BASE  0x10004
#define NAMED_COMP0_MAP4_OUTPUT_REF   0xA54
#define NAMED_COMP0_MAP5_INPUT_BASE   0x5
#define NAMED_COMP0_MAP5_ID_COUNT     0x0
#define NAMED_COMP0_MAP5_OUTPUT_BASE  0x10005
#define NAMED_COMP0_MAP5_OUTPUT_REF   0xA54
#define NAMED_COMP0_MAP6_INPUT_BASE   0x6
#define NAMED_COMP0_MAP6_ID_COUNT     0x0
#define NAMED_COMP0_MAP6_OUTPUT_BASE  0x10006
#define NAMED_COMP0_MAP6_OUTPUT_REF   0xA54
#define NAMED_COMP0_MAP7_INPUT_BASE   0x7
#define NAMED_COMP0_MAP7_ID_COUNT     0x0
#define NAMED_COMP0_MAP7_OUTPUT_BASE  0x10007
#define NAMED_COMP0_MAP7_OUTPUT_REF   0xA54
#define NAMED_COMP0_MAP8_INPUT_BASE   0x8
#define NAMED_COMP0_MAP8_ID_COUNT     0x0
#define NAMED_COMP0_MAP8_OUTPUT_BASE  0x10008
#define NAMED_COMP0_MAP8_OUTPUT_REF   0xA54


#define NAMED_COMP1_MAP0_INPUT_BASE   0x0
#define NAMED_COMP1_MAP0_ID_COUNT     0x0
#define NAMED_COMP1_MAP0_OUTPUT_BASE  0x30000
#define NAMED_COMP1_MAP0_OUTPUT_REF   0xA54
#define NAMED_COMP1_MAP1_INPUT_BASE   0x1
#define NAMED_COMP1_MAP1_ID_COUNT     0x0
#define NAMED_COMP1_MAP1_OUTPUT_BASE  0x30001
#define NAMED_COMP1_MAP1_OUTPUT_REF   0xA54
#define NAMED_COMP1_MAP2_INPUT_BASE   0x2
#define NAMED_COMP1_MAP2_ID_COUNT     0x0
#define NAMED_COMP1_MAP2_OUTPUT_BASE  0x30002
#define NAMED_COMP1_MAP2_OUTPUT_REF   0xA54
#define NAMED_COMP1_MAP3_INPUT_BASE   0x3
#define NAMED_COMP1_MAP3_ID_COUNT     0x0
#define NAMED_COMP1_MAP3_OUTPUT_BASE  0x30003
#define NAMED_COMP1_MAP3_OUTPUT_REF   0xA54
#define NAMED_COMP1_MAP4_INPUT_BASE   0x4
#define NAMED_COMP1_MAP4_ID_COUNT     0x0
#define NAMED_COMP1_MAP4_OUTPUT_BASE  0x30004
#define NAMED_COMP1_MAP4_OUTPUT_REF   0xA54
#define NAMED_COMP1_MAP5_INPUT_BASE   0x5
#define NAMED_COMP1_MAP5_ID_COUNT     0x0
#define NAMED_COMP1_MAP5_OUTPUT_BASE  0x30005
#define NAMED_COMP1_MAP5_OUTPUT_REF   0xA54
#define NAMED_COMP1_MAP6_INPUT_BASE   0x6
#define NAMED_COMP1_MAP6_ID_COUNT     0x0
#define NAMED_COMP1_MAP6_OUTPUT_BASE  0x30006
#define NAMED_COMP1_MAP6_OUTPUT_REF   0xA54
#define NAMED_COMP1_MAP7_INPUT_BASE   0x7
#define NAMED_COMP1_MAP7_ID_COUNT     0x0
#define NAMED_COMP1_MAP7_OUTPUT_BASE  0x30007
#define NAMED_COMP1_MAP7_OUTPUT_REF   0xA54
#define NAMED_COMP1_MAP8_INPUT_BASE   0x8
#define NAMED_COMP1_MAP8_ID_COUNT     0x0
#define NAMED_COMP1_MAP8_OUTPUT_BASE  0x30008
#define NAMED_COMP1_MAP8_OUTPUT_REF   0xA54

#define IOVIRT_RC_NUM_MAP             4
#define IOVIRT_SMMUV3_0_NUM_MAP       2
#define IOVIRT_SMMUV3_1_NUM_MAP       2
#define IOVIRT_SMMUV3_2_NUM_MAP       2
#define IOVIRT_SMMUV3_3_NUM_MAP       2
#define IOVIRT_SMMUV3_4_NUM_MAP       3
#define IOVIRT_NAMED_COMP0_NUM_MAP    9
#define IOVIRT_NAMED_COMP1_NUM_MAP    9
#define IOVIRT_MAX_NUM_MAP            33

/* DMA platform config parameters */
#define PLATFORM_OVERRIDE_DMA_CNT   0

/*Exerciser platform config details*/
#define TEST_REG_COUNT              10
#define EXERCISER_ID                0xED0113B5
#define PCIE_CAP_CTRL_OFFSET        0x4// offset from the extended capability header

/* Exerciser MMIO Offsets */
#define INTXCTL         0x004
#define MSICTL          0x000
#define DMACTL1         0x08
#define DMA_BUS_ADDR    0x010
#define DMA_LEN         0x018
#define DMASTATUS       0x01C
#define PCI_MAX_BUS     255
#define PCI_MAX_DEVICE  31
#define PASID_VAL       0x020
#define ATSCTL          0x024
#define ATS_ADDR        0x028
#define TXN_TRACE       0x40
#define TXN_CTRL_BASE   0x44
#define PCI_MAX_BUS     255
#define PCI_MAX_DEVICE  31

#define DVSEC_CTRL      0x8
#define PCI_EXT_CAP_ID  0x10
#define PASID           0x1B
#define PCIE            0x1
#define PCI             0x0
#define DVSEC           0x0023
#define AER             0x0001

/* PCI/PCIe express extended capability structure's
   next capability pointer mask and cap ID mask */

#define CLR_INTR_MASK       0xFFFFFFFE
#define PASID_TLP_STOP_MASK 0xFFFFFFBF
#define PASID_VAL_MASK      ((0x1ul << 20) - 1)
#define PASID_VAL_SHIFT     12
#define PASID_LEN_SHIFT     7
#define PASID_LEN_MASK      0x7ul
#define PASID_EN_SHIFT      6
#define DMA_TO_DEVICE_MASK  0xFFFFFFEF

/* shift_bit */
#define SHIFT_1BIT             1
#define SHIFT_2BIT             2
#define SHIFT_4BIT             4
#define SHITT_8BIT             8
#define MASK_BIT               1
#define PREFETCHABLE_BIT_SHIFT 3
#define ERR_CODE_SHIFT         20
#define FATAL_SHIFT            31
#define ERROR_INJECT_BIT       17

#define MSI_GENERATION_MASK (1 << 31)

#define NO_SNOOP_START_MASK 0x20
#define NO_SNOOP_STOP_MASK  0xFFFFFFDF
#define PCIE_CAP_DIS_MASK   0xFFFEFFFF
#define PCIE_CAP_EN_MASK    (1 << 16)
#define PASID_EN_MASK       (1 << 6)

/* PCIe Config space Offset */
#define BAR0_OFFSET        0x10
#define COMMAND_REG_OFFSET 0x04
#define CAP_PTR_OFFSET     0x34
#define PCIE_CAP_OFFSET    0x100


#define RID_CTL_REG    0x3C
#define RID_VALUE_MASK 0xFFFF
#define RID_VALID_MASK (1ul << 31)
#define RID_VALID      1
#define RID_NOT_VALID  0
#define ATS_TRIGGER    1
#define ATS_STATUS     (1ul << 7)
#define TXN_INVALID    0xFFFFFFFF
#define TXN_START      1
#define TXN_STOP       0

#define PCIE_CAP_CTRL_OFFSET 0x4// offset from the extended capability header

/* Memory config */
#define PLATFORM_OVERRIDE_MEMORY_ENTRY_COUNT        0x4
#define PLATFORM_OVERRIDE_MEMORY_ENTRY0_PHY_ADDR    0x1050000000
#define PLATFORM_OVERRIDE_MEMORY_ENTRY0_VIRT_ADDR   0x1050000000
#define PLATFORM_OVERRIDE_MEMORY_ENTRY0_SIZE        0x4000000
#define PLATFORM_OVERRIDE_MEMORY_ENTRY0_TYPE        MEMORY_TYPE_DEVICE
#define PLATFORM_OVERRIDE_MEMORY_ENTRY1_PHY_ADDR    0xFF600000
#define PLATFORM_OVERRIDE_MEMORY_ENTRY1_VIRT_ADDR   0xFF600000
#define PLATFORM_OVERRIDE_MEMORY_ENTRY1_SIZE        0x10000
#define PLATFORM_OVERRIDE_MEMORY_ENTRY1_TYPE        MEMORY_TYPE_RESERVED
#define PLATFORM_OVERRIDE_MEMORY_ENTRY2_PHY_ADDR    0x80000000
#define PLATFORM_OVERRIDE_MEMORY_ENTRY2_VIRT_ADDR   0x80000000
#define PLATFORM_OVERRIDE_MEMORY_ENTRY2_SIZE        0x60000000
#define PLATFORM_OVERRIDE_MEMORY_ENTRY2_TYPE        MEMORY_TYPE_NORMAL
#define PLATFORM_OVERRIDE_MEMORY_ENTRY3_PHY_ADDR    0xC030000
#define PLATFORM_OVERRIDE_MEMORY_ENTRY3_VIRT_ADDR   0xC030000
#define PLATFORM_OVERRIDE_MEMORY_ENTRY3_SIZE        0x20000
#define PLATFORM_OVERRIDE_MEMORY_ENTRY3_TYPE        MEMORY_TYPE_NOT_POPULATED

/** End config **/
